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LERA DDS Quality controlNot tested: CLK output voltage (use oscilloscope). Should be a square wave at 12.5 MHz of 2.7 V on 50 Ohm load. If instead it is 800 mV on 50 Ohm load, please open DDS and return board clkbuf06.pcb to Hawaii for exchange against a replacement board that has the correct voltage. Serial DDS-1-04 (Mexico)
1. Checklist
2. Power supply measurements (use EDAC 10953A 12 V 80 W adapter only)
3. Program DDS Connect USB to linux, check that /dev/ttyUSB{0,1,2,3} appear, open screen to each of them and check red/green LED blink on FTDI board. Verified: VVVV For production, the Vectron clock is used /4 at 25 MHz, and the LO-BUF board is used to distribute the clock to the DDS boards. DO NOT connect the 50 MHz output of the Vectron directly to the DDS, as there may be issues with the correct KP setting at boot time. Primary and secondary DDS, reset to factory default and clear parameter memory: CLR S Power cycle and check with frequency meter that they both output 8.8817842 MHz, the default of 10 MHz scaled by the clock ratio. Then, proceed with programming. Primary DDS, record commands: F1 13.454503886769 Fd 0.000000002147 Td 1 Tr 52428799 M 3 A D VQ 3600 VI 3600 S QUE string: 000000000C3C9EECBFB1000000000000000000000863031FFFFF000001104A87600E100E10000FFF Secondary DDS, record commands: KP 10 F0 13.454593958762 M 0 S QUE string: 000000000C3CA44B236A00000000000000000000000000000005000000004A00400FFF0FFF000FFF 4. Signals measurements and adjustments Frequency meter: Clock: temporarily set jumper to VCO on, using Rb external clock and frequency counter, set back to VCO off after tuning
RF power meter: Mini Circuits PWR-SEN-6G+ USB power sensor Note: terminate all back panel open connectors with 50 Ohm while measuring
VQ 3630 S QUE string 000000000C3C9EECBFB1000000000000000000000863031FFFFF000001104A87600E100E2E000FFF Oscilloscope on 1 MOhm input:
Disable clock VCO, power cycle and verify that it comes back with all the parameters OK: V 9 October 2015
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