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principles projects CNMI-Guam old projects |
LERA DDS software and programmingThe LERA DDS has a back-panel USB port, to be connected to the linux computer. Internally, there is a 4-port FTDI serial server. Port 1 loops back to the back-panel, and is intended to connect to the serial console of the D-Tacq. Port 2 is reserved for future GPS use. Port 3 connects to the auxiliary DDS module. Port 4 connects to the primary DDS module. The FTDI chip requires no driver in linux. Direct communication from linux Open two terminal windows. Connect the first one to the primary DDS module: screen /dev/ttyUSB3 19200 and the second one to the secondary DDS module: screen /dev/ttyUSB2 19200 Commands are given in the DDS8m manual from Novatech. The only commands useful to operate the LERA are:
Programs and activates the mode of the AD9854 chip; x=0 for constant frequency, and x=3 for chirping. Always set to zero constant frequency before programming the chirp. In the description of F0, F1 and Fd below, with the internal DDS module clock of 2^48/10^7 MHz, XX.XXXXXXXXXXXX is the exact output frequency, down to the μHz. With the external stock Vectron clock of 10^8/4 MHz, since the DDS module controller has no way of knowing the actual external clock frequency, one must "cheat" the Novatech controller by entering an output frequency multiplied by the ratio of internal to external frequencies, and by the ratio of PLL multipliers, i.e. (2^48/10^7)/(10^8/4)*10/10 or 1.125899906842624, thus to program F0 at 16.000000000000 MHz, enter F0 18.014398509482.
Sets the frequency of the constant frequency mode. On the primary DDS, we usually set F0 0.0, which will turn off the signal in mode M=0. On the secondary DDS, to allow 80 Hz offset for calibration, we usually program F0=F1-80 Hz, which, with the correction factor, is -0.000090719926. The secondary DDS is also used to demodulate and make the audio feedback. It can be set at any frequency within the chirp bandwidth, resulting in slightly different sounds as the chirp transects the fixed demodulation frequency, but we usually use the same -80 HZ offset as for calibration.
Sets the start frequency of the chirp mode. Apply the same scaling as for F0.
Sets delta frequency, for each chirp increment, to the nearest μHz. Decimal point required and needs all 12 decimal places. Apply the same scaling as for F0.
Sets the time at each frequency step Fd; integer from 0 to a maximum of 2^20-1 or 1048575. The unit is AD9854 system clock cycles (XO after applying PLL multiplier, or 3.55ns for the internal clock and 4ns for the external Vectron clock).
Sets the chirp length: the repeated duration of the frequency ramp starting at F1, in steps of Fd, at time intervals Td, until Tr times out, repeating continuously from F1; integer between 5 and 2^32-1 (4294967295), in AD9854 update clock cycles (system clock cycles * 2, or 7.1ns for the internal clock and 8ns for the external Vectron clock).
Disable the square-wave TTL output. We do not need it, so it is best left disabled.
Set the output level from 0 to 4095. There can be up to 1 dB difference between I and Q: to properly equalize, set VI 3600, then adjust VQ for identical output level. The on-board potentiometer can then be adjusted for exact power level (from -1 dBm to +7 dBm). 
Sets the PLL reference multiplier constant of xx for the AD9854 chip. Power-up default is KP 10 (0A in Hexadecimal). This must be one Hex byte as two characters. Legal values are 1 (bypass PLL) and 4 to 20 ( 01, 04 to 14 in Hexadecimal). This command must first be issued at the initial power up if connecting an external clock higher than 30 MHz to the DDS module; clock*kp cannot exceed 300 MHz or overheating damage to the chip will occur. Use a KP of 05 if using the Vectron precision OCXO divided to 50 MHz (experimental), a KP of 0A (10) (default) if using one of the Vectron OCXO devided to 25 MHz (default), Ilco TCXO of 24.197908 (external, WERA-compatible) or 28.147498 MHz (internal, Novatech-installed), and a KP of 14 (20) if using a 10 MHz Rubidium or GPS clock. Note: we have had erratic behaviour of the DDS after issuing the KP command. As it comes to KP 10 as default, we recommend that KP not be used explicitely before further experimenting.
Saves current state into EEPROM to be used as default upon next power up or reset.
Resets to saved state.
Restores factory default: F0 10 MHz if using internal clock; on the 25 MHz external clock, default is 8.8817842 MHz. Always follow by a S command to ensure that all registers are properly cleared, then power cycle.
Queries the status and parameters of the DDS module controller. Returns a hexadecimal string which can be converted using gnome-calculator; see Ifremer Python scripts for decoding. Summary: 000000001BCD35A8587900000000000000000000325401900000000001104A87600E100DCD000FFF ........|<---F1--->||<---F0--->||<---Fd--->||<-Tr->||<Td>|..KP.M..|VI||VQ|...... Example of sequence to program the primary DDS module to chirp 100 kHz at 12 (11.95 to 12.05) MHz driven by the 25 MHz Vectron clock; the parameters are obtained by running the matlab code dds_prog.m: F1 13.454503886769 FD 0.000000002202 TR 51118080 TD 1 M 3 This will result in a chirp length of 51118080 update clock steps, or 408.9 ms, and an effective bandwidth of 99.97 kHz. The choices of Fd, Tr and Td are critical to the performance of the radar, and are discussed fully in the LERA principles page. The following combinations are recommended; MT is the samples/chirp as defined in the WERA header, and F0 is F1-80 Hz for calibrations and audio feedback.
Freq. BW. wchirp F0 (F1-80Hz) F1 Fd Td Tr MT MHz kHz s ____________________________________________________________________________________________________ 8.250 50 0.52 0.000000000894 1 62914560 3072 2^10*3 12.000 100 0.4[3] 13.900575577403 13.900482519779 0.000000002218 1 52428800 2560 2^9*5 12.100 100 0.4[3] 0.000000002147 1 52428800 2560 2^9*5 13.500 100 0.4[3] 15.645220102908 15.645313160533 0.000000002218 1 52428800 2560 2^9*5 16.046 100 0.325 0.000000002863 1 39321600 1920 2^7*3*5 16.200 100 0.325 18.785914938109 18.786007995733 0.000000002958 1 39321600 1920 2^7*3*5 16.275 100 0.325 0.000000002863 1 39321600 1920 2^7*3*5 24.500 250 0.325 28.353546163405 28.353639221030 0.000000007388 1 39321600 1920 2^7*3*5 25.155 300 0.21[6] 29.086230777255 29.086323834880 0.000000013312 1 26214319 1280 2^8*5 27.300 300 0.21[6] 0.000000012884 1 26214400 1280 2^8*5 Note 1: the custom Vectron clock will fold the 60 Hz intermodulation exactly the same way as a WERA clock. Note 2: the chirp length wchirp must be entered in the wera header for proper wera16_raw_sort processing.
Freq. BW. wchirp lchirp F0 (F1-80Hz) F1 Fd Td Tr MT MHz kHz s s ____________________________________________________________________________________________________ 8.250 50 0.52 0.503316 9.260616805773 9.260526733781 0.000000000894 1 62914560 3072 2^10*3 12.000 100 0.4[3] 0.419430 13.454593958762 13.454503886769 0.000000002147 1 52428800 2560 2^9*5 12.100 100 0.4[3] 0.419430 13.567183949447 13.567093877454 0.000000002147 1 52428800 2560 2^9*5 16.046 100 0.325 0.314573 18.009984981848 18.009894909855 0.000000002863 1 39321600 1920 2^7*3*5 16.200 100 0.325 0.314573 18.183193423516 18.183283495508 0.000000002863 1 39321600 1920 2^7*3*5 16.275 100 0.325 0.314573 18.267635916529 18.267725988522 0.000000002863 1 39321600 1920 2^7*3*5 27.300 300 0.21[6]0.209715 30.568092398785 30.568182470777 0.000000012884 1 26214400 1280 2^8*5 Note 1: the stock Vectron clock frequency does not yield the exact WERA A/D frequency after division, therefore it is not possible to ensure at the same time WERA-compatiblity for processing, and folding of the 60 Hz intermodulation to exactly 0-Doppler. In the table above, the default WERA chirp lengths are used. Note 2: the actual chirp length lchirp must be entered in the wera header for proper wera16_raw_sort processing.
Freq. BW. wchirp lchirp F0 F1 Fd Td Tr MT MHz kHz s s ____________________________________________________________________________________________________ 13.500 100 0.447552 0.433193 15.143263675041 15.143353747033 0.000000002079 1 54149109 2644 2^2*611 16.200 100 0.335833 0.325058 18.183193423516 18.183283495508 0.000000002770 1 40632320 1984 2^6*31 16.200 224.5 0.335833 0.325058 18.112950278991 18.113040350984 0.000000006228 1 40632279 1984 2^6*31 ??? 16.100 100 0.335833 0.325058 18.126898428174 18.126988500166 0.000000002770 1 40632279 1984 2^6*31 WHOI 27.300 300 0.223437 0.216269 30.568092398785 30.568182470777 0.000000012494 1 27033600 1320 2^3*3*5*11 NOT WORK 27.300 300 0.223945 0.216760 30.568092398785 30.568182470777 0.000000012466 1 27095040 1323 3^3*7^2 26.310 224.5 0.223776 0.2165965 29.495798337170 29.495888409163 0.000000009347 1 27074554 1322 2*611 Note 1: the stock Vectron clock frequency does not yield the exact WERA A/D frequency after division, therefore it is not possible to ensure at the same time WERA-compatiblity for processing (i.e. use one of the default WERA chirp lengths), and folding of the 60 Hz intermodulation to exactly 0-Doppler. The folding can only be approximate; the exact MT for 1280 would be 1322.43. Experimentation need to be done with fractional MT. Note 2: computing the parameters with dds_prog is iterative. First, set l_chirp to be the exact desired length that folds 60 Hz to 0-Doppler. Second, obtain the corresponding MT and round to the nearest integer. Third, compute back what l_chirp would give this integer MT, and the corresponding FD and TR. Note 3: the actual chirp length lchirp must be entered in the wera header for proper wera16_raw_sort processing. Note 4: CAUTION! for compression to proceed (/16 etc...), one must ensure that MT contains the compression ratio as factors. If not, then the compressed data will not respect chirp boundaries, and any further processing will require interpolating back to the pre-compressed time series. pf 12 feb 19: only PPK seem to fail this requirement Importing to WERA The wera software must be given the true chirp length lchirp in seconds. If this is not done, the Doppler shifts will be erroneous, and there will be a "sinkhole" effect with the currents converging to the radar. This effect is a good diagnostic of an erroneously programmed conversion chirp length. The following steps need to be taken in wera_import:
In the header prepended to the WERA RAW file, enter the real frequency after FREQUENZ, the real chirp rate lchirp after RATE:, and the number of lf clock samples per chirp after MT:, from the table above.
from the table above, enter the number of lf clock samples per chirp after MT=. Communication through Python scripts Louis Marie from Ifremer, has written a python program that communicates with the DDS modules and decodes their hexadecimal output. Contact louis.marie@ifremer.fr. Using the SOF-8 program from Novatech This program requires a Windows XP computer with the FTDI drivers. Its advantage is that the replies from the DDS modules are translated to engineering units, and that corrections can be made for the external clock frequency. Using this program from a standalone Windows XP netbook can be useful for debugging. However, a fundamental flaw is its unability to deal with successive new FTDI servers. Windows assigns an incremental COM port number for each new server, while the buggy SOF-8 software refuses to deal with COM port numbers above 19. The program and drivers are found in the software repository. |