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LERA DDS Quality control

Not tested: CLK output voltage (use oscilloscope). Should be a square wave at 12.5 MHz of 2.7 V on 50 Ohm load. If instead it is 800 mV on 50 Ohm load, please open DDS and return board clkbuf06.pcb to Hawaii for exchange against a replacement board that has the correct voltage.

Serial DDS-1-02 (Mexico)

  • VECTRON serial number: 2154246-0016
  • Novatech primary serial: 20
  • Novatech secondary serial: 19
  • LO-BUF board: 02
  • LO-DIST board: 02
  • power supply board: 02

1. Checklist

  • DC input ferrite (tied down): V
  • fan shroud (glued down): V
  • clock grounding strap: V
  • USB FTDI grounding strap: V
  • VGA board clears LO-DIST board: V
  • IQ cables from DDS-1 to LO-DIST same length: V
  • adjust auxilary heater to minimum (CW): V
  • solid contacts at crimped connectors: V
  • heatsink clued to each DDS: V
  • thermal foam under and in front of clock bell: V
  • heat shrink at 12 V splitter: V
  • tape marking 12 V and 5 V on cables to LO-DIST and LO-BUF boards: V
  • relay control connected to BNC: V
  • front panel fiber optics blink: V
  • fan and velcro, tied down at (11,11.5) cm: V
  • jumpers
    • serial enable, DDS1 and DDS2 boards: VV
    • external clock, DDS1 and DDS2 boards: VV
    • VCO disable, CLK board: V
    • external clock, LO-BUF board: V
    • triple, 2/22 dBm TX output, on 22 dBm, glued, LO-DIST board: V
    • TUF source internal, LO-DIST board: V
    • 0-Ohm resistance on divide by 2, LO-BUF board: V

2. Power supply measurements

(use EDAC 10953A 12 V 80 W adapter only)

  • DC voltage 12 V input: 12.03 V
  • DC voltage 5V PSU output (V): 4.88 V
  • DC voltage -5V PSU output (V): -4.74 V
  • DC current reading (A): 1.67 A (clock warmed up, chirping)
  • AC power reading (A): 23.8 W
  • temperature brass bell/air: 40/23 C

3. Program DDS

Connect USB to linux, check that /dev/ttyUSB{0,1,2,3} appear, open screen to each of them and check red/green LED blink on FTDI board. Verified: VVVV

For production, the Vectron clock is used /4 at 25 MHz, and the LO-BUF board is used to distribute the clock to the DDS boards. DO NOT connect the 50 MHz output of the Vectron directly to the DDS, as there may be issues with the correct KP setting at boot time.

Primary and secondary DDS, reset to factory default and clear parameter memory:

 CLR
 S

Power cycle and check with frequency meter that they both output 8.8817842 MHz, the default of 10 MHz scaled by the clock ratio. Then, proceed with programming.

Primary DDS, record commands:

 F1 13.454503886769S
 F1 13.900482519779
 Fd 0.000000002147
 Fd 0.000000002218
 Td 1
 Tr 52428799
 Tr 52428800
 M 3
 A D
 VQ 3600
 VI 3600
 S

QUE string:

 000000000C3C9EECBFB1000000000000000000000863031FFFFF000001004A87400FFF0FFF000FFF

Secondary DDS, record commands:

 F0 13.454593958762
 F0 13.900575577403
 M 0
 S 

QUE string:

 000000000C3CA44B236A00000000000000000000000000000005000000004A00400FFF0FFF000FFF

4. Signals measurements and adjustments

Frequency meter:

Clock: temporarily set jumper to VCO on, using Rb external clock and frequency counter, set back to VCO off after tuning

  • adjust VCO to 50.000000 MHz: V
  • check auxiliary DDS1 and DDS2 clock output 25 MHz: VV
  • check Trig chirp length to match programmed DDS1: 2.3841868Hz
  • check D-Tacq clock output 12.5 MHz: V
  • check bandwidth on spectrum analyzer: 100 kHz centered at 12.000 MHz

RF power meter: Mini Circuits PWR-SEN-6G+ USB power sensor

Note: terminate all back panel open connectors with 50 Ohm while measuring

  • probe on I1=I2, adjust DDS1 I channel so that output is -3 dBm OK
  • probe on TX, adjust LO-DIST pot so that output is +18 dBm OK
  • enable calib mode, adjust DDS2 so that output is +18 dBm OK
  • probe on Q1=Q2, adjust DDS1 Q channel so that output is -3dBm, in software with VQ command:
 VQ 3500
 S

QUE string

 000000000C3C9EECBFB1000000000000000000000863031FFFFF000001004A87600E100DAC000FFF

Oscilloscope on 1 MOhm input:

  • Audio out adjust to max. gain CCW: 104 mVpp
  • Trig, check pulse on SMA: 4.70 Vpp 980us

Disable clock VCO, power cycle and verify that it comes back with all the parameters OK: V

pf jue may 14 03:07:36 UTC 2015

Reprogrammed to 24.5 MHz

F0 = 28.353546163405319

F1 = 28.353639221030068

Td = 1

Tr = 26214391

Fd = 0.000000011082

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Page last modified on May 14, 2015, at 03:09 am